The present invention is a dual-gate MOS device which is well suited for use in high voltage (i.e., around 15 volts) circuits, such as the high voltage circuitry used in EEPROM (electrically erasable and programmable read only memory) devices. The use of high voltages in EEPROM devices, primarily during programming of the memory's cells, can cause a problem known as gated diode breakdown. Gated diode breakdown occurs when a transistor is off and a high voltage is applied to its source or drain, which causes the PN junction to be strongly reverse biased The voltage on the gate of the transistor which causes the transistor's channel to be closed also generates an electrical field that decreases the breakdown voltage of the diodes associated with the drain and source regions.
The present invention overcomes this problem by separating the gate which turns off the transistor from the drain diffusion on which the high voltage is applied. As a result, the breakdown voltage of the diode formed by the drain and transistor channel is the normal breakdown voltage for such junctions.
The present invention is also suitable for use in amplifier circuits, such as cascode circuits, in which it is extremely important for the channel length of the transistor to be well controlled and consistent from device to device.